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M48Z08 M48Z18
5V, 64 Kbit (8Kb x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM AND POWER-FAIL CONTROL CIRCUIT UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z08: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48Z18: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V SELF-CONTAINED BATTERY IN THE CAPHATTM DIP PACKAGE PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 8K x 8 SRAMs RoHS COMPLIANCE Lead-free components are compliant with the RoHS Directive.
Figure 1. 28-pin CAPHAT, DIP Package
28 1
PCDIP28 (PC) Battery CAPHATTM
Rev 5.0 December 2005 1/16
M48Z08, M48Z18
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 28-pin CAPHAT, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....3 .....4
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 13 Table 11. PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z08, M48Z18
SUMMARY DESCRIPTION
The M48Z08/18 ZEROPOWER(R) RAM is a 8K x 8 non-volatile static RAM which is pin and functional compatible with the DS1225. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. Figure 2. Logic Diagram
VCC
It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48Z08/18 silicon with a long life lithium button cell in a single package. Table 1. Signal Names
A0-A12 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Supply Voltage Ground Not Connected Internally
13 A0-A12 M48Z08 M48Z18
8 DQ0-DQ7
E G
W E G
W VCC VSS NC
VSS
AI01022
Figure 3. DIP Connections
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M48Z08 22 M48Z18 21 8 9 20 10 19 11 18 12 17 13 16 14 15
AI01183
VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48Z08, M48Z18
Figure 4. Block Diagram
A0-A12
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
8K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
VCC
VSS
AI01394
OPERATION MODES
The M48Z08/18 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of Table 2. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD(min)(1) VSO(1) 4.75 to 5.5V or 4.5 to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 12 for details.
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M48Z08, M48Z18
READ Mode The M48Z08/18 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be Figure 5. READ Mode AC Waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01385
available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next address access.
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Symbol tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX Parameter(1) READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 5 10 5 50 40 M48Z08/M48Z18 Unit Min 100 100 100 50 Max ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF.
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M48Z08, M48Z18
WRITE Mode The M48Z08/18 is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01386
tWHAX
tWHQX
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A12 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
tELEH
tEHAX
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M48Z08, M48Z18
Table 4. WRITE Mode AC Characteristics
Symbol tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH tAVEH tWHQX(2,3) Parameter(1) WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable 1 Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable 1 High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable 1 High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition 80 80 10 M48Z08/M48Z18 Unit Min 100 0 0 80 80 10 10 50 30 5 5 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48Z08, M48Z18
Data Retention Mode With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z08/18 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 8.) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z08, M48Z18
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 5. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
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M48Z08, M48Z18
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M48Z08 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5
M48Z18 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5
Unit V C pF ns V V
Figure 9. AC Testing Load Circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 30pF
CL includes JIG capacitance
AI01398
Table 7. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M48Z08, M48Z18
Table 8. DC Characteristics
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Min Max 1 1 80 3 3 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected.
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M48Z08, M48Z18
Figure 10. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS
RECOGNIZED
tDR tFB tRB DON'T CARE
tR tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running.
Table 9. Power Down/Up AC Characteristics
Symbol tPD tF(2) tFB(3) tR tRB trec Parameter(1) E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time E or W at VIH before Power Up Min 0 300 10 0 1 2 Max Unit s s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD VSO tDR(3) Parameter(1,2) M48Z08 Power-fail Deselect Voltage M48Z18 Battery Back-up Switchover Voltage Expected Data Retention Time 11 4.2 4.3 3.0 4.5 V V YEARS Min 4.5 Typ 4.6 Max 4.75 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25C, VCC = 0V.
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M48Z08, M48Z18
PACKAGE MECHANICAL INFORMATION
Figure 11. PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note: Drawing is not to scale.
Table 11. PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150 inches
13/16
M48Z08, M48Z18
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M48Z 08 -100 PC 1 TR
Device Type M48Z
Supply Voltage and Write Protect Voltage 08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 18 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed -100 = 100ns
Package PC = PCDIP28
Temperature Range 1 = 0 to 70C
Shipping Method blank = ECOPACK Package, Tubes TR = ECOPACK Package, Tape & Reel
Note: 1. The M48Z08/18 part is offered with the PCDIP28 (e.g., CAPHATTM) package only.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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M48Z08, M48Z18
REVISION HISTORY
Table 13. Document Revision History
Date March 1999 19-Jul-01 19-Dec-01 21-Dec-01 20-May-02 10-Sep-02 01-Apr-03 28-Aug-04 14-Dec-05 Version 1.0 2.0 2.1 2.2 2.3 2.4 3.0 4.0 5.0 First issue 2-socket SOH and 2-pin SH packages removed; reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10) Remove all references to "clock" Changes to text to reflect addition of M48Z08Y option Modify reflow time and temperature footnotes (Table 5) Remove all references to "SNAPHAT" and M48Z08Y part (Figure 2; Table 5, 6, 3, 4, 10, 12) v2.2 template applied; updated test condition (Table 10) Reformatted; removed references to `crystal' (Figure 1) Updated template, Lead-free text, removed footnote (Table 8, 12) Revision Details
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M48Z08, M48Z18
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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